The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
FIG. 1 illustrates an example of resistor-capacitor (RC) network 100 that includes, among other elements, a high resistance (high-R) resistor 102 and a metal-oxide-silicon (MOS) capacitor 104 that includes a high-k metal gate 106 (where k is a dielectric constant and the high-k is with respect to the dielectric constant of silicon dioxide). High resistance is generally in a range of 100 to 2000 ohms/square, while high-k typically refers to a k value that is generally in a range of 4.0 to 100.0. Thus, the MOS capacitor 104 is generally referred to as a high-k metal gate (HKMG) MOS capacitor. The high-R resistor 102 is located on a shallow trench isolation portion 108. Thus, as can be seen, the RC network 100 generally has a fairly wide profile.
When creating HKMG MOS capacitors 104, and more particularly, an RC network 100 with modern transistors, a gate-last based HKMG integration scheme generally requires strict polysilicon density requirements due to the multiple chemical mechanical planarization (CMP) processes involved in the formation of the high-k metal gate 106. The metal gate density requirement limits the HKMG MOS capacitor 104 density per given area. This can become a major concern for high performance, low cost circuit design. A typical HKMG manufacturing process generally only offers RC networks that include high-R resistors that are formed on shallow trench isolation portions adjacent to MOS capacitors, which, as previously noted, results in the RC network having a fairly wide profile.
Prior to the HKMG embodiment of RC networks, a polysilicon gate was formed on a diffusion layer to provide a MOS capacitor. In moving to the current generation of HKMG MOS capacitors, in order to achieve the same capacitance, the area required for the MOS capacitor increases in size due to the aforementioned CMP requirements for the high-k metal gate 102. FIG. 2 illustrates an example of the transition from a polysilicon gate MOS capacitor 200 to an HKMG MOS capacitor arrangement 202. As can be seen in FIG. 2, to achieve the same capacitance in the HKMG MOS capacitor arrangement 202 as in the polysilicon gate MOS capacitor 200, four HKMG MOS capacitors 104 are needed. Thus, as can be seen in FIG. 2, a high-R resistor 102 and HKMG MOS capacitor 104 arrangement in RC networks 100 generally results in a layout area increase, thus increasing the cost of a chip that includes such RC networks.